Design A Csi2 Receiver Controller Camera Raspi V2 With Two Data Lanes

Abstract

As a rise of the current market of camera CMOS image sensors, display driver ICs, application processor for mobile devices create a great demand of communication interface which ensure large bandwidth, high speed with low power and the minimum number of the data bus. However, the data flow cannot drive directly between protocol layers. Whilst “common parallel interfaces are difficult to expand, require many interconnections, and consume relatively large amounts of power” .With the vision to establish standards for hardware and software interfaces, MIPI (Mobile Industry Processor Interface) alliance has presented CSI-2 (Camera Serial Interface) which uses D-PHY (physical layer) standard. These standards provide high speed, low power operations with a small number of lanes to connect between camera sensors and a host processor. By the above advantages, they were applied in many applications, especially in mobile and wearable devices. “Design a CSI-2 Receiver Controller” project is carried out to be embedded into a CSI-2 receiver subsystem which is a connector between the PHY layer and the upper layer. In detail, this subsystem can get image data from Raspberry camera via PPI (Physical Protocol Interface), then process and propagate those data to UART for other processing purposes.