Research and implement of eCPRI packet processing module for fronthaul network on FPGA in 5G-NR gNodeB base station

Abstract

In the last few decades, Mobile Wireless Communication networks have experienced a remarkable change and generally refer to a change in the nature of system, speed, technology, frequency, data capacity, latency etc. The journey of Mobile Wireless Communication has never stopped evolving from 1G followed by 2G, 3G, 4G, and the latest technology 5G due to the massive demand of human kinds. The duty of upcoming 5G is to ease the pressing of increased bandwidth and range as well as decreased latency and cost. Fronthaul is associated with a new and different type of Radio Access Network architecture consisting of centralized Baseband Units (BBUs) and Remote Radio Units (RRUs)[2] . In order to meet the 5G challenges of increased traffic and data flows, a new connection protocol for the fronthaul network called Evolved Common Public Radio Interface (eCPRI)[1] has been published. As industry bodies consider new network architectures, a key consideration is the functional split that separates layers between the BBUs and the RRUs. However, the more the split options are shifted to the left, the less the amount of data transmitted across the interface which can ease the load for the BBUs. Furthermore, the required data rate at each split options is decreased as it move to the left and as the split options move to the left, the data format is no longer IQ samples. Because of the increase in scale of 5G, a more efficient fronthaul interface is needed. This has led to a paradigm shift in fronthaul network design, targeting greater flexibility and efficiency by moving to a packet – switched network using the mature and widely available Ethernet as the transport base. This thesis is carried out to handle the need in fronthaul transport network by designing a system that supports eCPRI to transmit data from the BBUs to RRUs in 5G Radio Access Network. By referencing the specification of eCPRI, we develop a hardware system on FPGA to encapsulate and extract required headers for this protocol. The system is compatible with a 10G Ethernet subsystem that provides 10Gbps Ethernet MAC and a Physical Interface. On top of the system, we develop drivers and applications to configure and run the system.