Design pseudo 2 – port sram memory – 28nm

Abstract

Static random access memory (SRAM) is a critical embedded part of most modern VLSI system-on-chip (SoC). Static random access memory (SRAM) is the solution often chosen by its large memory capacity and low power consumption. SRAM is a type of semiconductor memory that uses bistable latching circuitry (flip-flop) to store each bit. Data stored on SRAM is only a temporary means that data will disappear when the power is turned off. SRAM is also easier to use than DRAM. "Design Pseudo 2-port SRAM Memory" project is carried out with the aim to capture, better understand integrated circuit technology (ASIC), deeply designed for SRAM memory. Furthermore, this project intends to response the requirement of customer: improve performance, reduce the area, low power consumption, and frequency greater than 500 MHz for SRAM memory. The design consists of four blocks CTL, I/O, DECODE and MEMORY. In this project, our team builds a high performance and low power consumption Pseudo-2-Port (P2P) SRAM using the TSMC 28nm process. To meet the criteria of small area, high performance and low power consumption, P2P SRAM technique, and the 6T bitcell are used. To accomplish this project, our team need to understand the structure and functions of SRAM memory. At the same time, it is possible to analyze the schematic and timing concept. Besides, we need to apply the knowledge learned about SRAM to be able to build and analyze Pseudo 2-port (P2P) SRAM memory. The project Pseudo 2-port (P2P) SRAM memory circuit is implemented in a TSMC 28nm process. This circuit operates over the temperature range from -40oC to 125oC with supply voltage 0.9V ± 10% and with corners SS, TT, FF