Power optimization In physical design on interface module of a graphic chip Using tsmc 28nm technology

Abstract

The interface module is a critical block which part of most modern VLSI system-on-chip (SoC). Currently, the integrated module occupies large area of mobile application processors. Because of the requiment of reducing area and saving energy on SoC for mobile applications, designing high density and low power consumption devices is essential. In this project, our team builds a interface module design which is essential in commercial project of synapse company, using TSMC 28nm Technology. To meet the criteria of extremely decline power consumption, VTH decreasing technique and controling fan-out and cappacitance are used, which requires specific additional Timing report to ensure correct functions. As this design is developed in a small die and flexiable hard macros, it is necessary for TSMC 28nm technology to be applied in physical design. The result of this project is an extremely save power consumption, using dynamic and leakage power methods which developed in TSMC 28nm technology. A full set of schematics and report with meet requiment of customers. Because of the important of saving power consumption in every device, This project is contributed not only designed but also applied into the electronic devices.