NAND Flash Memory Verification Using Universal Verification Methodology

Abstract

Recently, with the rapid growing speed of mobile devices usage in both quality as well as quantity, the requirement for memory that could be able to be stored, written, erased data with a high rate and big capacity is a critical issue that can result in the competitiveness of an electronic product. With these aims, the essential goal of this thesis is to focus on analyzing, studying as well as verifying the structure of the NAND-FLASH memory in transferring the data in term of read, write and erase functionalities by using the Universal Verification Methodology which also known as UVM standard. Within this decay, the NAND memory, an electronic (solid-state) non-volatile computer storage medium that can be electrically erased and reprogrammed, was developed by Toshiba and commonly used inside memory cards, USB flash drives etc due to its advantages in endurance within a relatively small number of write cycles in a specific block. In this thesis, we study a new product in the NAND flash memory which supports 3 different modes of interface and a larger internal data move which can read 4MB/s. To handle this project, we firstly analyzed the whole structure of the device and then started to build the environment follow the UVM flow. Up-to-date, we completed the design verification flows to test the Register Transfer Level model (RTL) for all commands that supported by this device.