Design least recently used (LRU) cache on FPGA to speed up Ethernet packet classification applications in 5G Core

Abstract

Common network devices store data matching to ethernet packets in flow tables, each flow is identified by 5-Tuple headers. An efficient mechanism is needed to classify packets by flow. Using FPGA is one of the solutions to speed up Flow Classification applications. The topic serves as a basis to increase the efficiency of handling large numbers of packets on 5G UPF. A User Plane Function (UPF) is a basic network function in the Fifth Generation Core (5GC) architecture that performs many services such as flow identification and packet processing. The logic of each service is glued around a flow table. In this project, we present a design of flow table cache offloading using a Field Programmable Gate Array (FPGA) solution. Our design replaced the entries in cache by LRU algorithm and the cache is 4-ways set associative then the number of hit cases was improved. When lookup requests go to the cache, they are processed in a pineline process then the performance is one packet per clock cycle so this reaches the high speed requirement of the 5G network. The flow table cache follows the LRU rules which will choose the least recently used entries in the table to replace when inserting new entries. For objective evaluation, we use the ZC706 board to test the unit module in the flow table cache, evaluate each module work and test the flow table cache top. First, we evaluate the functional correctness of the cache then we evaluate the performance of the cache.