A compact high-speed pseudo differential self-bias receiver design for high bandwidth Die to die phy

Abstract

This thesis proposed a circuit design for the compact high-speed self-bias differential receiver under the process node of 10nm with 0.9V I/O voltage and 0.75V core voltage. The result proved that the circuit could perform better with twice as much as the expected frequency specification of 1Ghz. Finally, the netlists from layout were used for post-layout simulation to identify the causes that leaded to deficient results and further analysis for optimizing the whole design