Design a synchronous pseudo 2-port read/write memory 1024x32mux4 28nm technology

Abstract

Static random-access memory (SRAM) is a critical embedded part of most modern VLSI system-on-chip (SoC). It is a type of semiconductor memory that uses bistable latching circuitry (flip-flop) to store each bit. Static random access memory (SRAM) is the solution often chosen by its fast speed, stability and low power consumption. Data stored on SRAM is only a temporary; it means that data will disappear when the power is turned off.

In our thesis - Design synchronous pseudo 2-port Read-Write memory 1024x32 mux4 - our team has built a high performance and low power consumption Pseudo-2-Port SRAM using the technology 28nm process. To meet the criteria of small area, high performance and low power consumption, the 6T bit cell and some design techniques (folding SRAM, pre-decoder and so on) are used.

To accomplish this project, our team need to understand the structure SRAM memory both top-view and leaf-cell level. Meanwhile we investigate its operation by draft the true table and data flow. The project Pseudo 2-port (P2P) SRAM memory circuit is implemented in a 28nm process. This circuit operates over the temperature range from –40℃ to 125℃ with supply voltage 0.9V ± 10% and with corners SS, TT, FF.