Delay-locked loop (dll) training for high- speed data transactions

Abstract

In recent years, the Moore’s law has been slowing and the evolution of AI has necessitated the development of very strong chips. The chips are connected together to do more functionalities and process a huge volume of data. In high-speed data transmission between different parts of the integrated circuit or system becomes more prevalent, the proper functioning of system often greatly depends on precise signal alignment. The Delay-Locked Loop (DLL) is used to create a delayed version of a clock signal, in which the delay value is fixed regardless of temperature, voltage or the process of the chip. In order to prevent the timing violation when transferring data between chips, we need a training system which combines with the DLL to find the optimal point of data. The algorithm developed in this thesis will address the limitation of cross-chip data transmission using the Delay-Lock Loop (DLL) design. The DLL Training design uses the algorithm by running the data quality check with the purpose of finding the optimal point by locating the left and right edges of data. This design will concentrate on the Architecture, Register-Transfer Level (RTL), Design Verification and making the output quality in performance or ATPG coverage. The DLL design poses an important role in today’s Microchip Industry. However, without a proper system to put it in use, engineers cannot fully utilize the ability of this design. Our training design has successfully controlled the DLL design and achieved a stable functionality that could satisfy today’s high-speed design expectations by passing through an adequate range of test cases and simulations.