Design a 14nm io impedance calibration block for high speed interface double datarate application

Abstract

The main objective of the thesis is to design the IO impedance calibration for high – speed interface that used 14 nm technology. The purpose of the IO impedance calibration is to calibrate the electronic signal, reduce the alter from process, voltage and temperature variations. Two basic types of the IO impedance calibration architecture used are digital block and analog block. The digital block is to generate the RTL code for the analog block, while the analog block will do the calibration process with output driver to drive the signal with the expected current 18mA ± 10% and the comparator to compare the voltage level. This thesis presents an IO impedance calibration block to achieve the expected current, reduce the delay time, increase the speed of transmitting data and apply for double data – rate. The IO impedance calibration block is designed and simulated in Custom Complier of Synopsys using mode 14 nm. This thesis proposes a circuit design for IO impedance calibration block for high speed interface for double data – rate application. We also propose a layout design for the comparator.