Low power design on vlsi layout developed in 28nm technology

Abstract

Over the last two decades, low-power design has become a concern in digital VLSI design, especially for portable and high performance systems. As Technology scales into the Deep Sub-Micro (DSM) regime, standby sub-threshold leakage power increases ex-potentially with the reduction of the threshold voltage. Due to the increasing emergence of energy-constrained electronic devices, it is more important to suppress energy consumption to achieve a longer battery life, effective leakage min-imitations techniques are becoming a necessity. Therefore, there are demands for design methods for less energy consumption. Based on applications integrated circuit and designed to be of different types like high density, high performance, and low power. In this project, our aim is to design and implement two methodology Multi threshold voltage and Multi-bit flop developed on 28nm technology. We later optimize and change the multi voltage group cells and merge the single to multi-bit flop as well as reducing power consumption and leakage current in our design. These methods will be characterized and the performance of them is compared against before and after applying. The characteristics will be done using Synopsys tool simulations. The method will be designed and optimized with the following consideration on order of importance: power and speed. Power: power consumption such as leakage power and dynamic power ought to be optimized to get the highest efficiency. Reducing operation voltage is also an effective way to reduce circuit power consumption but is degrades the noise margin Speed: Applying the method multi-bit is designed and implemented at 28nm technology and observed that based on the characteristic of each technique we can be optimized to obtain the target parameter, specially is reducing cell delay time.