Design a high speed Delay locked loop in tsmc 28nm

Abstract

Delay Locked Loop (DLL) has been widely used for designing high-speed memory interface circuit such as Clock Distribution. The DLL is a simple means of providing a programmable clock delay between input and output to provide for clock synchronization. In order to supply a clock with a synchronized edge, in situations where the latency at the time of design is unknown, a simple, selectable approach is to insert a DLL to provide a programmable delay between the input clock and the desired output clock. Each block can then be independently synchronized after the final circuitry is assembled.

There are two main parts of DLL including Master and Slave. Each parts is divided into analog and digital part. The master DLL precisely calculates the clock period and adjusts this calculation across voltage and temperature The Slave DLL configures the delay as a precise fraction of the reference clock period. In this thesis, we focus on designing the circuit as well as the layout of Slave DLL because the Slave DLL is used for anywhere in circuit that clock need to be changed, meanwhile the Master DLL is only used once.

This thesis proposes a circuit design for the Slave DLL in TSMC 28nm process. We also propose a layout design for the Delay Line block of Slave DLL