Register-transfer level Design with Universal Verification Methodology for Configurable Two Width Search and Write Ternary Content Addressable Memory

Abstract

Computer architects are opposing a bewildering variety of memory-types to choose from when implementing memory related concept to the hardware. In fact, many data processing applications nowadays, such as address matching or broadcasting, require items to be searched in some data structure stored in the memory, which is exorbitantly inefficient if the memory is very large or the search algorithm is relatively inefficient for conventional RAM. Therefore, the demand for an innovative memory that can utilize data structure is rising enormously. A proposed solution is called associative memory or content addressable memory (CAM), in which the stored data can be identified for access by the content of the data itself rather than by an address. In fact, CAM’s processing time is significantly boosted due to its memory is accessed simultaneously in parallel on the basis of the data content, rather than sequential searching in RAM. In this project, we study Capstone Project “Register-transfer Level Design with Universal Verification Methodology for Configurable Two Width Search and Write Ternary Content Addressable Memory” under the guidance of PhD. Huỳnh Việt Thắng and Eng. Nguyễn Chí Tân. The project includes Design and Verification parts, which are assigned to Nguyễn Minh Thái and Huỳnh Việt Thống respectively. Up-to-date, the project is completed by successfully built a functioning Ternary Content Addressable Memory that conforms Savarti’s specification, fully functional tested by Universal Verification Methodology.