Design A High-Speed Receiver With Continuous Time Linear Equalizer (CTLE)

Abstract

In today’s society, the fast-growing technological industry requires cutting-edge advancements and innovations for executing high-execution frameworks for various applications relating to handling high-speed information transmission. Such applications as hyper-scale datacentres, 5G and machine learning are dependable for organizing, preparing, and transmitting expensive sums of information. In this manner, it is vital to design an integrated circuit in a multi-die chip that can perform high-speed communication between die to die. Regarding the interconnection between dies inside a chip, I/O (input/output) cells is an interface which oversees this task, combining devices (such as a transmitter, and receiver) for controlling the transferring of data. This thesis aims to design the receiver (RX) as it plays an important role in accepting the signal transmitted from the die, comparing, amplifying, and increasing the magnitude of the signal connected to its input to yield further stages. The methodology suggested in the thesis for designing a compact high-speed receiver uses CTLE (Continuous Time Linear Equalizer) technique. To convert the output from the CTLE block to a single-ended rail-to-rail signal, the second block called CML-to- CMOS (Current Mode Logic to Complementary Metal-Oxide Semiconductor) is used to convert to a digital signal. The frequency is aimed at 4GHz with the data rate’s frequency being at 8Gbps. Layout designs along with layout techniques are implemented to minimize the non-ideal factors. This thesis the circuit design for the compact high-speed receiver under the process node of GF12. Finally, the netlist from the pre-layout is used for post-layout simulation to identify the causes that led to deficient results and further analysis for optimizing the whole design.