Design a calibration and control block for the Delay-locked loop (DLL) design

Abstract

When transmitting high-frequency data, especially when the data is transmitted on both edges of the clock signal, we must be able to control the delay of the clock signal in comparison with data signal(s). This delay value is also required to be fixed once it is locked, the purpose is to make the clock to be able to capture data at the most stable point. In analog design, there is a design called Delay Locked Loop (DLL). The DLL block is created for that purpose, but for that block to be functional, there is a need for a controller. In this project, we will focus on the controller of the DLL block creating a delayed version of a signal, in which the delay value is fixed regardless temperature, voltage or the process of the chip. From the specification of the DLL block the circuit engineer provided, we must design a controller to make sure it meets requirement of the circuit and has some functions of the controller, making the controller calibrates the DLL block in the real-time environment (temperature, voltage, etc.), controls the delay of the clock as required, makes sure the clock signal is free of glitch during calibration and running time.