Design a high-speed duty cycle adjustment

Abstract

In this thesis we propose a design to adjust the duty cycle of the clock signal by adjusting the slew rate of clock signal. Method to adjust slew rate is controlling the transistors’ status which means turning on or off devices to adjust the charged current hence adjusting the slew rate of clock signal. We apply method sweeping codes feeding to the DCA to control the devices. Layout designs and strategies are employed to reduce the non-ideal factors.