Power distribution network in VLSI layout – Analysis and Optimization of tsmc 28nm chip technology, 1.05v voltage supply

Abstract

With high performance mobile computing devices like tablets and smart-phones virtually swiping the VLSI chip market, the industry is facing the perpetual challenge of optimizing between power and performance, more than ever before Power distribution networks deliver the power and the ground voltages from pad locations to all devices in a design. Shrinking device dimensions, faster switching frequency and increasing power consumption in deep submicron technologies cause large switching currents to flow in the power and ground networks. Rapidly switching currents cause spatial and temporal fluctuations in the supply voltage which may cause functional failures in a design (IR drop effect), degrade circuit performance (EM effect) and create reliability concerns. A robust power distribution network is essential to ensure reliable operation of circuits on a chip. Power-supply integrity verification is, therefore, a critical concern in high-performance designs. We then implemented simple ways based on changing width and pitch of the metal lines in the power metal layers to reduce the effect of IR drop and EM. The increase in the width of metal lines could ease the magnitude of resistance in voltage drop while leveling up the number of metal lines give the better performance Fixing the DRC error and the displacement of metal lines and standard cell give the better performance of chip and decrease the power consumption of thr whole chip.