Quality management for Single Port Embedded Memory Compiler design

Abstract

We live in the 4.0 era, where almost every daily job is related to machines and electronic devices, resulting in an increasing demand for products by users both in terms of products and services function and form, leading to optimization from even the smallest components and one of them is memory. A testament to this development is that the transistors in electronic components manufactured today are 20 times faster and occupy 1% less space than transistors made 20 years ago. Both technical and manufacturability requirements are a challenge in memory production. However, the number of devices per memory and system performance has improved exponentially over the past two decades. However, the strict requirements of high speed, high performance but low power consumption requirements, besides reducing the area but increasing the number of transistors and requiring all transistors to Good performance and the reduction of design time, costs and resources have brought significant obstacles. Contradictory requirements aimed at improving memory have made the design and manufacturing process prone to errors, making it easy to create low-quality products. To avoid that, there must be a team dedicated to quality control before starting the design, after each design stage and before delivery to the customer, which is one of the main jobs of QA/QC engineer. In order to serve QA/QC work, this project will focus on building a system called Management Quality Assurance system. The system with checklists is clearly divided for each stage of memory development with 2 main phases: Front-end and Back-end phase suit with development flow. The results obtained from the checklists are presented in the form of report pass/fail and this result will reflect the quality of the memory being managed.